AMD Zen 3 core Arcitecure based Next-Gen Ryzen 4000 ‘Vermeer’ processors Detailed -Up To 16 Cores / 32 Threads, 32 MB Shared L3 Cache Per CCD, 8 Cores Per CCX

Recently, We got Official information regarding AMD’s next-generation Ryzen 4000 CPU based on the Zen 3 core architecture that has been unveiled. The information is part of confidential AMD documents shared by the CyberCatPunk.
The documents provide us some new information regarding the AMD next-gen 4000 CPU while reiterating a few bits and pieces that we’ve known for a while now. The AMD Vermeer Desktop Processor family is known as the AMD Family 19h Model 21h B0. According to the confidential AMD documents, The AMD Zen 3 core architecture based Ryzen 4000 AM4 processors family, codenamed Vermeer, is designed for use in high-performance desktop platforms & will feature up to two Core/Cache Complex Dies (CCD’s) and a single I/O Die ( IOD).
The previous-gen design where each CCD is comprised of two CCX’s, and in the Zen 3 CCD will consist of a single CCX that will feature 8 cores and that can run in either a single-thread mode or a two-thread model for up to 16 threads per CCX. Since the chip houses a maximum of two CCDs, the core and thread count will max out at 16 cores and 32 threads which is the same as the existing flagship AM4 desktop Processor AMD Ryzen 9 3950X.
Each Zen 3 core architecture will feature 512 KB of L2 cache for a total of 4 MB of L2 cache per CCD (Core/Cache Complex Dies) and That should equal 8 MB L2 cache on a dual CCD CPU. Along with the L2 cache, each core/Cache Complex Dies will also comprise up to 32 MB of shared L3 cache. For Zen 2 core, the L3 cache was split between the two CCX’s with each CCX having their own separate Up To 16 MB cache. The size of the cache remains the same per core/Cache Complex Dies (CCDs) but now all cores can share a larger number of L3 cache.
Core Complex Die (CCD):
  • Consists of one CCX
  • The CCX consists of:
  • Up to 8 cores where each core may run in single-thread mode (1T) or two-thread SMT mode (2T)
  • for a total of up to 16 threads per complex
  • 512KB of L2 per core for a total of 4MB L2 per CCD
  • Up to 32MB of L3 shared across all cores within the complex
The AMD Ryzen 4000 ‘Vermeer” Desktop processors with Zen 3 core architecture will introduce a slightly improved scalable data fabric, supporting up to 512 GB per DRAM channel or up to 1 TB of ECC DRAM. The AMD Ryzen 4000 Desktop CPUs will retain native DDR4-3200 speeds For the memory interface. There will be 2 unified memory controllers on the CPU, each supporting a single DRAM channel for a total of 2 DIMMs per channel. The following are the details for the I/O and PCH feature set for the IOD:
Scalable Data Fabric. This provides the data path that connects the compute complexes, the I/O interfaces, and the memory interfaces to each other.
  • Handles request, response, and data traffic
  • Handles probe traffic to facilitate coherency, supporting up to 512GB per DRAM channel
  • Handles interrupt request routing (APIC)
  • Scalable Control Fabric. This provides the data path that provides a configuration access path to all blocks
  • Handles configuration request, response, and data traffic
  • GMI2: Up to two special Data Fabric ports, for connections to the CCDs.
Memory interface
  • 2 Unified Memory Controllers (UMC), each supporting one DRAM channel
  • 2 DDR4 Phys. Each PHY supports:
  • 64-bit data plus ECC
  • 1 DRAM channel per PHY
  • 2 DIMMs per channel
  • DDR4 transfer rates from 1333MT/s to 3200MT/s
  • UDIMM support
PSP and SMU
  • MP0 (PSP) and MP1 (SMU) microcontrollers
  • This document refers to the AMD Secure Processor technology as Platform Security Processor (PSP).
  •  Thermal monitoring
  • Fuses
  • Clock control
NBIO
  • PCI Device ID information uses Vendor ID is 1022h for all devices (see Table 18 [PCI Device ID
  • Assignments.].
  • 2 SYSHUBs
  • 1 IOHUB with IOMMU v2.x
  • Two 8×16 PCIe controllers supporting Gen1/Gen2/Gen3/Gen4. Note that SATA Express is supported by combining an x2 PCIe® port and two SATA ports on the same 2 lanes.
  • 24 total lanes combo PHY, UPI muxing
Fusion Controller Hub (FCH or southbridge (SB))
  • ACPI
  • CLKGEN/CGPLL for refill generation
  • GPIOs (varying number depending on muxing)
  • LPC
  • Real-Time Clock (RTC)
  • SMBus
  • SPI/eSPI
  • Azalia
  • High Definition Audio
  • Up to 2 lanes of SATA Gen1/Gen2/Gen3, also provides the legacy SATA support for SATA
  • ports. Shared with PCIe
  • SGPIO
  • USB3.1 Gen2
  • 4 ports, includes support for legacy USB speeds
AMD is expected to unveil its next-generation Ryzen 4000 series desktop AM4 processors lineup based on the Zen 3 core architecture on 8th October as confirmed in an official announcement.

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